1. Field of the Invention
The present invention relates to the input of a logic gate and, more particularly, to an edit structure that allows the input of a logic gate to be changed by modifying any one of the metal or vias masks used to form the metal interconnect structure.
2. Description of the Related Art
Logic circuits commonly include gates that have an input that is permanently connected to a logic high, or permanently connected to a logic low. Conventionally, the input of a logic gate was permanently connected to a logic high by connecting the input directly to a power supply line. Similarly, the input of a logic gate was permanently connected to a logic low by connecting the input directly to a ground line.
More recently, however, with sub-micron circuits, it is undesirable to permanently connect the input of a logic gate directly to the power supply line or the ground line. This is because the voltage and current spikes that can be present on the power supply line and the ground line can permanently damage the logic gate.
As a result, sub-micron circuits commonly use a “tie-in” circuit that connects the input of a logic gate to either a power supply line or a ground line. A tie-in circuit can be implemented in a number of different ways. One common method of implementing a tie-in circuit is as a polysilicon resistor structure.
FIGS. 1A-1D show views that illustrate an example of a prior-art tie-in circuit 100. FIG. 1A shows a plan view, while FIGS. 1B-1D show cross-sectional views taken along lines 1B-1B through 1D-1D, respectively, of FIG. 1A. As shown in FIGS. 1A-1D, tie-in circuit 100 includes a semiconductor material 110, such as a non-conductive region formed in single-crystal silicon.
In addition, as further shown in FIGS. 1A-1D, tie-in circuit 100 includes a polysilicon strip 112 that touches the top surface of semiconductor material 110, and a first isolation layer 114 that touches the top surfaces of semiconductor material 110 and polysilicon strip 112. Tie-in circuit 100 also includes a first contact 120 that extends through first isolation layer 114 to make an electrical connection to a first end of polysilicon strip 112, and a second contact 122 that extends through first isolation layer 114 to make an electrical connection to a second end of polysilicon strip 112.
Further, tie-in circuit 100 includes spaced-apart metal-1 strips 124 and 126. Metal-1 strip 124 has a first end connected to first contact 120, and a second end connected to the input of a logic gate. Metal-1 strip 126, in turn, is a two pronged structure that includes a base 126B that is connected to second contact 122, a first prong 126F, and a second prong 126S.
In the FIGS. 1A-1D example, first prong 126F is connected to a power supply line 130, and second prong 126S is spaced apart from a ground line 132. Thus, in the FIGS. 1A-1D example, the connection of first prong 126F to power supply line 130 defines tie-in circuit 100 as a “tie-high” circuit because one end of the circuit is connected to the input of the logic gate, while the other end of the circuit is connected to power supply line 130.
During the testing and evaluation of a semiconductor chip, it is often necessary to modify one of the logic circuits by changing the logic state that is permanently applied to the input of a logic gate. One common approach to changing the logic state that is permanently applied to the input of a logic gate is simply to change the tie-in circuit.
For example, to change the logic state placed on the input of a logic gate from a permanent logic high to a permanent logic low, the tie-in circuit can simply be changed from a tie-high circuit to a tie-low circuit. This change can be implemented by simply modifying the metal-1 mask so that first prong 126F is spaced apart and electrically isolated from power supply line 130, and second prong 126S is connected to touch ground line 132.
The FIGS. 1A-1D example illustrates a tie-in circuit where the end connected to the input of the logic gate, and the end connected to the power supply line (or ground line) are provided by the first metal layer (metal-1). Tie-in circuits, however, are commonly implemented with the ends connected to other metal layers. For example, the end connected to the input of the logic gate, and the end connected to power supply line 130 (or ground line 132) can be implemented in the fourth metal layer (metal-4).
FIGS. 2A-2D show views that illustrate an example of a prior-art tie-in circuit 200. FIG. 2A shows a plan view, while FIGS. 2B-2D show cross-sectional views taken along lines 2B-2B through 2D-2D, respectively, of FIG. 2A. Tie-in circuit 200 is similar to tie-in circuit 100 and, as a result, utilizes the same reference numerals to designate the elements which are common to both tie-in circuits.
As shown in FIGS. 2A-2D, tie-in circuit 200 is identical to tie-in circuit 100 except that tie-in circuit 200 also includes three more metal layers. More specifically, the metal-1 strips 124 and 126 are electrically connected to contacts 120 and 122, respectively, and electrically isolated from all other metal-1 structures.
In addition, tie-in circuit 200 further includes a second isolation layer 210 that touches the top surface of first isolation layer 114, a via 212 that extends through second isolation layer 210 to make an electrical connection to metal-1 strip 124, and a via 214 that extends through second isolation layer 210 to make an electrical connection to metal-1 strip 126. Further, tie-in circuit 200 includes spaced-apart metal-2 strips 220 and 222 that touch the top surface of second isolation layer 210. The spaced-apart metal-2 strips 220 and 222 are connected to vias 212 and 214, respectively, and electrically isolated from all other metal-2 structures.
Further, tie-in circuit 200 includes a third isolation layer 230 that touches the top surface of second isolation layer 210, a via 232 that extends through third isolation layer 230 to make an electrical connection to metal-2 strip 220, and a via 234 that extends through third isolation layer 230 to make an electrical connection to metal-2 strip 222. Further, tie-in circuit 200 includes spaced-apart metal-3 strips 236 and 238 that touch the top surface of third isolation layer 230. The spaced-apart metal-3 strips 236 and 238 are connected to vias 232 and 234, respectively, and electrically isolated from all other metal-3 structures.
Tie-in circuit 200 also includes a fourth isolation layer 240 that touches the top surface of third isolation layer 230, a via 242 that extends through fourth isolation layer 240 to make an electrical connection to metal-3 strip 236, and a via 244 that extends through fourth isolation layer 240 to make an electrical connection to metal-3 strip 238. Further, tie-in circuit 200 includes spaced-apart metal-4 strips 246 and 248 that touch the top surface of fourth isolation layer 240. The metal-4 strips 246 and 248 are connected to vias 242 and 244, respectively.
The metal-4 strips 246 and 248 are identical to metal-1 strips 124 and 126, respectively, with metal-4 strip 248 having a two pronged structure that includes a base 248B that is connected to via 244, a first prong 248F, and a second prong 248S. In the FIGS. 2A-2D example, first prong 248F is connected to a power supply line 250, and second prong 248S is spaced apart and electrically isolated from a ground line 252.
One of the disadvantages of tie-in circuits 100 and 200 is that each tie-in circuit has an input and an output that are associated with specific metal layers, regardless of which metal layer is used. The disadvantage of being associated with a specific metal layer is that if the tie-in circuit must be changed, then the mask associated with that specific metal layer must be changed, even if that is the only change to the mask.
For example, with tie-in circuit 100, to change the logic state placed on the input of a logic gate from a permanent logic high to a permanent logic low, the metal-1 mask must be modified so that first prong 126F is spaced apart and electrically isolated from power supply line 130, and second prong 126S is electrically connected to ground line 132, even if there is no other change to the metal-1 mask.
Modifying masks is an expensive and time consuming procedure. As a result, if the only modification to a mask was to change the state of a tie-in circuit, then the modification of the tie-in circuit becomes quite expensive.